`timescale 1ns/1ps

module led_demo_tb;

reg sys_clk;
reg sys_rst_n;
wire led;

/*iverilog */
initial
begin            
    $dumpfile("wave.vcd");        //生成的vcd文件名称
    $dumpvars(0, led_demo_tb);    //tb模块名称
end
/*iverilog */

initial
begin
    sys_clk = 1'b0;
    sys_rst_n = 1'b0;
    #60
    sys_rst_n = 1'b1;
    #1000 //仿真执行1000ns
    $stop; //必须要这个，iverilog停止仿真
end

always #10 sys_clk = ~sys_clk;

led_demo led_demo_ut0 (
    // Inputs
    .sys_clk(sys_clk),
    .sys_rst_n(sys_rst_n),

    // Outputs
    .led( led)
);

endmodule